In the fabrication of integrated circuitry, numerous devices are packed into small areas of a semiconductor substrate and interconnected to create an integrated circuit. Many of the individual devices are electrically isolated from one another. Accordingly, electrical isolation is an integral part of semiconductor device design for preventing unwanted electrical coupling between the adjacent components and devices. For example, interlayer/interlevel dielectric layers isolate structures from metal interconnect layers. Such may be required to fill very narrow gaps between adjacent structures, for example gaps which have high aspect ratios (ratio of depth to average width) where the features are also spaced close together. Insulative structures such as shallow trench isolation regions are also formed in recesses (trenches) within substrate material between components.
Common electrical isolation/insulative materials include doped and undoped silicon oxide-comprising materials. Silicon oxide-comprising dielectric materials may be deposited in a number of different manners, including chemical vapor deposition and plasma enhanced chemical vapor deposition. With the increase in aspect ratio between adjacent features, use of flowable materials such as spin-on dielectrics is increasing due to greater gap filling capability than from chemical vapor deposition methods. Such flowable processes include applying a liquid precursor solution of a silicon-containing polymer onto a spinning substrate. The substrate is then baked to remove solvent from the liquid, and thereby form an adhesive solid onto the substrate. Thereafter, the substrate is subjected to a thermal oxidizing ambient sufficient to oxidize the solid into the desired silicon oxide-comprising material.
One type of spin-on dielectric uses one or more polysilazanes as a starting precursor. Oxidation of polysilazane-containing spin-on dielectrics typically requires an underlying silicon dioxide layer deposited by decomposition of tetraethylorthosilicate (TEOS), particularly where such spin-on dielectrics are deposited into openings having high aspect ratios and closely spaced features (i.e., less than 75 nanometers. TEOS-deposited silicon dioxide facilitates oxidation of the lower/innermost portions of the polysilazane(s) within deep/high aspect ratio openings where the oxidizing ambient may not reach.
The TEOS-deposited silicon dioxide is typically deposited onto a silicon nitride layer which functions as a diffusion barrier. As spaced adjacent features continue to be moved closer together, it is becoming increasingly difficult to get both sufficiently thick TEOS-silicon dioxide layers and silicon nitride layers in between adjacent features to provide their respective functions. Elimination or thinning of the TEOS layer alone has been determined to provide inadequate complete oxidation of densified polysilazane-comprising spin-on dielectrics between very closely spaced adjacent features. Such can ultimately lead to shorts between contacts formed within openings of the resulting silicon oxide-comprising interlayer dielectrics. Accordingly, a need remains to address such issues.
While the invention was motivated from the above-identified challenges, the invention is in no way so limited in overcoming or addressing such challenges. Rather, the invention is only limited by the accompanying claims as literally worded and as appropriately interpreted in accordance with the doctrine of equivalents.